=The following additional information is provided to help identify the cause of error while running nativelink scripts=
Sourced NativeLink script /opt/Altera/intelFPGA_lite/17.0/quartus/common/tcl/internal/nativelink/modelsim.tclĮrror: Can't launch ModelSim-Altera Simulation software - make sure the software is properly installed and the environment variable LM_LICENSE_FILE or MGLS_LICENSE_FILE points to the correct license file.Įrror: NativeLink simulation flow was NOT successful Info: Starting NativeLink simulation with ModelSim-Altera software Quartus sim root : /opt/Altera/intelFPGA_lite/17.0/quartus/eda/sim_lib Quartus root : /opt/Altera/intelFPGA_lite/17.0/quartus/linu圆4/ Info: NativeLink has detected Verilog design - Verilog simulation models will be used Info: Start Nativelink Simulation process IOW, you can't keep the dialog box open to help find the file, you have to make note of where the file is, close the dialog box, then open the file. Meaning you have to make the dialog box go away before you can open the file it tells you to check for more information. where the error message says to check for more details) are only populated after you hit OK. Set Up a Project with the ModelSim-Altera Software (Command-Line)Ĭreated by chm2web html help conversion utility.Oddly, the contents of that file (i.e. Set Up a Project with the ModelSim-Altera Software To continue with the ModelSim-Altera simulation flow and perform a timing simulation, return to one of the following steps:
Refer to ModelSim software documentation for more information on how to view and interpret the results of the simulation. If you are simulating an ARM-based Excalibur design, the bus functional model generates the output.dat bus functional model simulation file. Perform the functional simulation in the ModelSim-Altera software. Select the top-level design file to simulate.
In the Name list, click the + icon to expand the work directory. Repeat step c to add the \ \altera\verilog\altera_mf\ directory. Specify the \ \altera\verilog\220model\ directory. In the Search Libraries (-L) box, click Add. If you are simulating a Verilog design, to specify the ModelSim precompiled libraries: If you are performing a functional simulation of an ARM ®-based Excalibur design, repeat steps 5b to 5d to compile the appropriate ARM-based Excalibur simulation model wrapper file.Ĭhoose Simulate (Simulate menu). Repeat steps 4b to 4d to compile the test bench file(s). In the Files of Type list, select All Files (*.*), and in the Look in list select the Verilog or VHDL Design File. In the File name list, type the directory path and file name of the Verilog or VHDL Design File. In the Library list of the Compile HDL Source Files dialog box, select the work library. To compile the Verilog or VHDL Design Files and test bench files (if you are using a test bench): If you want to use VHDL 87-compliant simulation libraries, you must map lpm and altera_mf to the \ \altera\220model_87\ and \ \altera\altera_mf_87\ directories, respectively. Repeat steps 3a and 3b to map altera_mf to the \ \altera\altera_mf\ directory. Type lpm in the Library Name box, and type \ \altera\vhdl\220model\ in the Library Maps to box, and click OK. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.įor VHDL 93-compliant designs, to map the design libraries to your work library: If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. In the Library Maps to box, specify the \quartus\eda\sim_lib\modelsim\ \altgxb\ directory.
Under Create, select a new library and a logical mapping to it. The Create a New Library dialog box appears. If your design contains the altgxb megafunction, to map to the precompiled Stratix GX functional simulation model libraries:Ĭhoose New > Library (File menu). Set Up a Project with the ModelSim-Altera Software. If you have not already done so, perform 2. To use the Model Technology ModelSim ®-Altera ® (OEM) software to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components: Set Up a Project with the ModelSim-Altera Software (Command-Line) Using the Quartus II Software with Other EDA Tools Using the ModelSim Software with the Quartus II Software